1. Field of the Invention:
The present invention relates to low temperature processes for forming back side redistribution layers for semiconductor devices. More particularly, the present invention relates to low temperature processing for back side redistribution layers as suitable for use in optically interactive semiconductor devices and other semiconductor devices, and resulting structures.
2. State of the Art:
Interconnection and packaging-related issues are among the factors that determine not only the number of circuits that can be integrated on a semiconductor die or “chip,” but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced sizes of transistors and enhanced chip performance. The industry has come to realize that merely having a fast chip will not necessarily result in a fast system. The fast chip must also be supported by equally fast and reliable electrical connections. Essentially, on-chip connections, in conjunction with those of the chip's associated packaging, supply the chip with signals and power, provide signals from the chip and redistribute the tightly spaced or pitched terminals or bond pads of the chip to the terminals of a carrier substrate, such as a printed circuit board.
Flip-chip technology is well known to those of ordinary skill in the art, as the technology has been in use for over 30 years and continues to develop. A flip-chip semiconductor device conventionally comprises a semiconductor die having an active surface having active integrated circuitry components formed therein and bearing contacts such as bond pads, and an opposing back surface devoid of active components or, usually, of any features whatsoever. A dielectric layer, for example, of silicon dioxide or silicon nitride, may be formed over the active surface by techniques well known in the art. Apertures may be defined in the dielectric layer (also termed a “passivation layer”) using well-known photolithographic techniques to mask and pattern the dielectric layer and etch the same with hydrofluoric acid to expose the contacts or bond pads on the active surface. The bond pads may be respectively connected to traces of a redistribution layer on the dielectric layer in the form of redistribution lines in a well-known manner, for example, by evaporating or sputtering a layer of aluminum or an alloy thereof over the passivation layer, followed by masking and etching the layer to define the traces. The redistribution lines of the redistribution layer enable the external connections of the semiconductor device provided by the relatively compact arrangement of closely spaced or pitched bond pads to be distributed over a larger surface area with wider spacing or pitch between external connections to higher-level packaging. Discrete conductive elements, such as solder bumps or balls, are typically placed upon a pad located at an end of each redistribution line to enable electrical connection with contact pads or terminals on the higher-level packaging, usually comprising a carrier substrate, such as a printed circuit board. The flip-chip semiconductor device, with the solder bumps on its active surface, is “flipped” and attached face down to a surface of the carrier substrate, with each solder bump on the semiconductor device being positioned on the appropriate contact pad or terminal of the carrier substrate. The assembly of the flip-chip semiconductor device and the carrier substrate is then heated so as to reflow the solder bumps to a molten state and thus connect each bond pad on the semiconductor device through its associated redistribution line and solder bump to an associated contact pad or terminal on the carrier substrate. Because the flip-chip arrangement does not require leads of a lead frame or other carrier structure coupled to a semiconductor die and extending beyond the lateral periphery thereof, it provides a compact assembly in terms of the semiconductor die's “footprint” on the carrier substrate.
Redistribution lines may also be located on the back side of a semiconductor die and electrically connected to the bond pads of the active surface through conductive filled vias that extend through the semiconductor die. U.S. patent application Ser. No. 10/209,823, entitled, “Semiconductor Dice Having Backside Redistribution Layer Accessed Using Through-Silicon Vias, Methods of Fabrication and Assemblies,” assigned to the assignee of the present invention and the disclosure of which is hereby incorporated by reference herein, teaches use of rerouting redistribution lines on a back side of a semiconductor die accessed from an active surface of a semiconductor substrate through vias. While such a redistribution layer may help reduce the necessary footprint from a semiconductor die and helps alleviate cross-talk between adjacent redistribution lines, the processing techniques employed do not accommodate the sensitive, easily damaged nature of the various components on the active surface.
For example, optically interactive semiconductor devices, such as complementary metal oxide semiconductor (CMOS) imagers, employ particularly temperature sensitive components in the form of microlenses disposed on their active surfaces, which begin to degrade at about 220° C. Semiconductor memory devices, while not as limiting with respect to temperature-induced damage, experience subsequent operational difficulties when exposed to temperatures of 250° C. and may sustain irreparable damage commencing at about 300° C. exposure.
Accordingly, a need exists for methods of fabricating back side redistribution lines and associated structures, such as conductive vias, that do not damage any of the active surface circuitry of a semiconductor device or components associated with such semiconductor devices.